Feature

●Function Description：The FT4232H is FTDI’s 5th generation of USB devices. The FT4232H is a USB 2.0 High Speed (480Mb/s) to UART/MPSSE ICs. It has the capability of being configured in a variety of industry standard serial interfaces
●The FT4232H has four independent configurable interfaces. Two of these interfaces can be configured as UART, JTAG, SPI, I2C or bit-bang mode, using an MPSSE, with independent baud rate generators. The remaining two interfaces can be configured as UART or bit-bang
●EEPROM Interface： When used without an external EEPROM the FT4232H defaults to a quad USB to an asynchronous serial port device. Adding an external 93C46 (93C56 or 93C66) EEPROM allows customization of USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT4232H for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Soft Pull Down on Power-Off and I/O pin drive strength.
●Asynchronous Bit-Bang Mode：Asynchronous Bit-Bang Mode：Asynchronous Bit-Bang mode is the same as BM-style Bit-Bang mode. On any channel configured in asynchronous bit-bang mode, data written to the device in the normal manner will be self-clocked onto the parallel I/O data pins (those which have been configured as outputs). Each I/O pin can be independently set as an input or an output. The rate that the data is clocked out at is controlled by the baud rate generator.
●Synchronous Bit-Bang Mode：With Synchronous Bit-Bang mode, data will only be sent out by the FT4232H if there is space in the FT4232H USB TXFIFO for data to be read from the parallel interface pins. This Synchronous Bit-Bang mode will read the data bus parallel I/O pins first, before it transmits data from the USB RxFIFO. It is therefore 1 byte behind the output, and so to read the inputs for the byte that you have just sent, another byte must be sent.


Description

Quad Multi-Purpose UART/MPSSE Controllers. The FT4232H has four independent UART/MPSSE Controllers. These blocks control the UART data or control the Bit-Bang mode if selected by the SETUP command. The blocks used on channel A and channel B also contain a MPSSE (Multi-Protocol SynchronousSerial Engine) in each of them which can be used independently of each other and the remaining UART channels. Using this it can be configured under software command to have 1 MPSSE + 3 UARTS (each UART can be set to Bit Bang mode to gain extra I/O if required) or 2 MPSSE + 2 UARTS.
USB Protocol Engine and FIFO control. The USB Protocol Engine controls and manages the interface between the UTMI PHY and the FIFOs of the chip. It also handles power management and the USB protocol specification.
Dual Port FIFO TX Buffer (2Kbytes per channel). Data from the Host PC is stored in these buffers to be used by the Multi-purpose UART/FIFO controllers. This is controlled by the USB Protocol Engine and FIFO control block