[Other]

USB Data acquisition Module
work in LINUX, Win2000 / XP / WIN7, Other common operating systems (If necessary provided in linux and Android driver to support ARM processors, etc.), provides DLL forVB.NET, VC, C ++ Builder, Dephi, LabVIEW, Matlab, Labwindows, QT ..., programming function interface is easy to use, easy to write applications, ProvidedLabVIEWRoutines and LabWindows routines.
Features:
         1, USB
USB2.0 High-speed bus transfer Easy to use, can be automatically configured to support hot-swappable plug and play devices
        2   Analog signal input Analog input channels: 16 Single-ended Input port pressure : -10--10V a?? input signal range : -10--10V (PGA = 1), - 5V-5V (PGA = 2), - 2.5V-2.5V (PGA = 4), - 2V- 2V (PGA = 5), - 1.25 V-1.25V ((PGA = 8), - 1V-1V ((PGA = 10), - 0.625V- 0.625V (PGA = 16) a?? Analog Input impedance : 100K a?? Resolution : 12Bit (4096) a?? The maximum total error : <0.2% a?? Programmable Gain : 1,2,4,5,8,10,16 a?? Sampling rate : 100sps-200Ksps ( multi-channel 100sps-100Ksps) Internal Clock 3  analog signal output a?? analog output channels : two single-ended a?? Analog output range : 0-10V a?? Analog output current: 5 mA a?? Resolution : 12Bit (4096) a?? nonlinearity error : ± 2LSB a?? scan clock : 1sps-1000Ksps internal clock 4 ,  digital signal input / output a?? Input / output channels: 8 a?? Input / output modes: full input / full output a?? Input Level : TTL or CMOS compatible a?? Output Level : CMOS 5, PWM measurement input a?? Number : 1 a?? Input voltage : 0-3.3V a?? Input Frequency : 1-200KHz a?? Input Duty Cycle: 1% - 99% a?? frequency and duty cycle measurement error: 1% 6 , the counter a?? The number of counters: 1 a?? Input Level : TTL or CMOS a?? Count bits: 32 ( maximum 65535 * 65535 ) 7, PWM output a?? PWM output channels: 2 a?? PWM Output Level : CMOS a?? Input Duty Cycle: 1% -